1. Field of the Invention
The present invention relates to a system verifying apparatus and method. More specifically, the present invention relates to an apparatus which verifies a system LSI (semiconductor integrated circuit) comprising a microprocessor, a memory, and the like.
2. Description of the Related Art
In recent years, to deal with more and more complicated systems, the degree of integration and the scale of LSIs have been increased. Thus, functional verification is consuming an inordinate amount of design cycle. One of papers says that as much as 70 percent of the design cycle is consumed by functional verification. In particular, a factor constituting a bottleneck to verification is creation of test programs.
FIG. 6 shows one of algorithms as to how a true data dependency is verified. That is, if any instruction uses a value produced by a previous instruction “div”, it must delay its decoding until the previous instruction produces a result itself. FIG. 7 shows one of examples of implementation using an MIPS(R)-like assembler. We used to create such a test program manually.
Although the functionality is effectively checked by these hand-crafted tests, the number of such test scenarios become enormous as the complexity of microprocessors increase, which becomes a bottleneck of the verification efforts.
One solution for this problem is to employ a “random test”. The “random test” is a method for creating sequences from a number of small sequences by arranging them randomly and checking the functionality by comparing the result between the design and the functional model.
The randomly-arranged test sequence is very effective in that the functionality and robustness of a system are exhaustively tested. It sometimes hits the scenarios that are too hard to produce or very complicated scenarios that are so hard for verification engineers to think of without making an effort in programming.
However, the random test is not a main effort in verification because it is hard to tell which test scenario has been covered by the random sequence.
Then, a test program such as the one shown in FIG. 7 must be manually created. Typically, in developing a system LSI, several hundred thousand to several million such test programs must be created.
Recently, an assertion-based simulation tool represents the next major advancement in a functional simulator for complex integration circuits. The assertion-based verification tool checks whether or not a designed logic circuit meets an operational specification for the system in connection with conditions established before or after events or always met conditions. The assertion language reduces the amount of description more than that of HDL implementation and can easily be instantiated in the design under verification to flag violations of specified functional design behavior. The assertion description language also facilitates checks on programs that may exhibit design bugs.
However, the assertion is inherently a language used to describe conditions for inhibited operations. Thus, in general, the assertion significantly improves the efficiency with which bugs are detected and a debug efficiency, but still requires operations of creating test programs. Consequently, even the assertion-based verification method cannot sufficiently reduce the amount of operations of creating test programs, which require the highest costs among the verifying operations.
Verification of the functions of the system proceeds in parallel with development of an LSI design. Setting of expected value data can be automated using an instruction set simulator created to develop software (a simulator relating to an instruction set). Further, 80 percent or more bugs can be checked using a program that randomly generates instructions. Thus, conventional random tests are desirably used effectively. However, verification using random tests makes it difficult to determine which item has been verified.